1. Field of the Invention
This invention relates to the field of digital-to-analog converters (DACs), and particularly to techniques for reducing switching noise in current switching DACs.
2. Description of the Related Art
A basic current switching DAC is shown in FIG. 1a. A plurality of current sources 10, 12 are connected to a analog output lines 14, 16 via pairs of switches 18, 20 and 22, 24. The switches are typically implemented with transistors, which are controlled using respective control signals 26, 28, 30, 32 provided by a latch circuit 34. Latch circuit 34 receives a digital input word via a set of input lines, as well as a clock signal.
The digital input word represents a desired analog output voltage. In operation, latch circuit 34 responds to an applied digital input word by setting control signals 26, 28, 30, 32, thereby switching selected current sources to selected output lines as needed to obtain the desired analog output voltage. Latch circuit 34 is clocked, such that control signals 26, 28, 30, 32 change state in synchronization with the applied clock.
The DAC's operation is illustrated in the timing diagram shown in FIG. 1b. The diagram depicts the applied clock signal, along with an ideal DAC output 35, and an actual DAC output 36. As can be seen, the actual DAC output exhibits a considerable amount of noise; this is caused by switching slew and glitches which arise when the control signals change state, disconnecting some current sources from the analog output lines and connecting others. This non-linear source of error can result in an unacceptable level of distortion in the DAC output.
The operation of even an ideal DAC results in a frequency dependent attenuation of the DAC output; this is seen in the output spectrum shown in FIG. 1c. For a typical current switching DAC as shown in FIG. 1a, the DAC's output signal power falls off at a rate given by
            sin      ⁡              (        x        )              x    ,where fCLK is the frequency of the applied clock signal and x is given by
            π      *      freq              f      CLK        ,where freq is the frequency of the DAC's analog output signal. This attenuation can necessitate the use of a correction filter, and can significantly limit the DAC's use in high frequency applications.
One approach to reducing noise caused by switching slew and glitches which arise when the current sources are switched is found in U.S. Pat. No. 6,812,878 to Jewett et al. As shown in FIG. 3 of Jewett, clocked resampling switches are interposed between the current source switches and the analog output lines. The resampling switches are operated such that the current source switches are temporarily disconnected from the analog output lines when the control signals change state, thereby preventing switching noise from reaching the output.
However, this approach also has drawbacks. For example, the resampling switches are implemented with transistors. Since the base nodes of the resampling switch transistors connected to the output line are clocked, clock noise can be coupled onto the analog output lines via the parasitic capacitances that exist across the terminals of the resampling switch transistors. In addition, in operation, the DAC's current sources are connected to ground for half of every switching cycle; as such, the DAC output power is half that of a conventional “non-return-to-zero” (NRZ) DAC, without any means to recover the lost power